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Pin Configuration
Figure 2. Package Diagram
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name
OVR
FB
CMP
VMIN
FO
PWM4
PWM3
PWM2
PWM1
ENA
ADIM
SLPR
REF
VCC
FB4
VDD
OUT4
CH4
FB3
OUT3
CH3
FB2
OUT2
CH2
FB1
OUT1
CH1
GND
Description
This pin is input for over-voltage regulation.
This pin is for feedback of minimum drain voltage of external current regulation switch. This
pin is externally connected to the cathode of the feedback photo-coupler.
This pin is for compensation of the minimum channel voltage feedback.
Synchronous signal of channel drain-voltage. If multiple controllers are operated, this pin
must be tied together . In single operation, this pin must be open.
This pin is fault output. In case of OLP, SLP, and OCP; this pin is connected to ground.
PWM dimming signal input pin of channel 4.
PWM dimming signal input pin of channel 3.
PWM dimming signal input pin of channel 2.
PWM dimming signal input pin of channel 1.
Enable input.
This pin is for the reference voltage of the LED current feedback voltage.
This pin is for setting the reference of channel over-voltage protection (short-LED protection).
This pin is the reference output. Voltage is 5V; current capability is 3mA.
This pin is the supply voltage of the controller.
This pin is for current sensing feedback of channel 4.
Internal gate driver power supply voltage. A large capacitor (1μF~2μF) must be connected
from this pin to ground.
This pin is for gate signal to the external balance FET of channel 4.
This pin is for drain voltage of the external balance FET of channel 4.
This pin is for current sensing feedback of channel 3.
This pin is for gate signal to the external balance FET of channel 3.
This pin is for drain voltage of the external balance FET of channel 3.
This pin is for current sensing feedback of channel 2.
This pin is for gate signal to the external balance FET of channel 2.
This pin is for drain voltage of the external balance FET of channel 2.
This pin is for current sensing feedback of channel 1.
This pin is for gate signal to the external balance FET of channel 1.
This pin is for drain voltage of the external balance FET of channel 1.
This pin is the ground.
? 2011 Fairchild Semiconductor Corporation
FAN7346 ? 1.0.0
3
www.fairchildsemi.com
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